= Register transfer level
{title2=RTL}
{wiki}
Register transfer level is the abstraction level at which computer chips are mostly designed.
The only two truly relevant RTL languages as of 2020 are: <Verilog> and <VHDL>. Everything else compiles to those, because that's all that <EDA vendors> support.
Much like a <C (language)> compiler abstracts away the <CPU> assembly to:
* increase portability across ISAs
* do optimizations that programmers can't feasibly do without going crazy
Compilers for RTL languages such as Verilog and <VHDL> abstract away the details of the specific <semiconductor physical implementation>[semiconductor technology] used for those exact same reasons.
The compilers essentially compile the RTL languages into a <standard cell library>.
Examples of companies that work at this level include:
* <Intel>. Intel also has <semiconductor fabrication plants> however.
* <Arm (company)> which does not have <fabs>, and is therefore called a "<fabless>" company.