= Address translation
Converting a <virtual address> to a <physical address> using the current <address space>'s mapping, with access checks. In <paging>, the <memory page> number changes while the offset within it stays fixed.
<Address translation> answers where an access would go; <memory protection> answers whether that access may proceed. Neither answer is the stored value. Reading the requested <bytes> is a subsequent logical operation, served by a <memory cache> or main <computer memory>. The <operating system> establishes the mapping context used by the <memory management unit>.<Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others/Mechanism: Address Translation>[Operating Systems: Three Easy Pieces, chapter 15, Mechanism: Address Translation, printed pp. 1–2: hardware mechanism and operating-system control]{ref}
Consider an original toy model with unsigned 12-<bit> <virtual addresses>, <byte> addressing, and 64-<byte> <memory pages> and <page frames>. Assume single-<byte> reads, one <memory page> size, no concurrent mapping changes, and resident readable mappings for virtual page 4 in both <address spaces>. The <virtual address> $v=\mathtt{0x12D}=301$ has six page-number <bits> and six offset <bits>, rather than a split between <hexadecimal> digits. By <Euclidean division>,
$$
301=4\cdot64+45,\qquad q=4,\qquad d=45=\mathtt{0x2D}.
$$
Process A maps virtual page 4 to <page frame> 13; process B maps it to <page frame> 9. Thus the identical <virtual address> denotes
$$
a_A=13\cdot64+45=877=\mathtt{0x36D},\qquad a_B=9\cdot64+45=621=\mathtt{0x26D}.
$$
These are addresses, not the <bytes> read there. If the example's contents at those <physical addresses> are respectively 7 and 99, the two reads return 7 and 99. The mapping calculation alone cannot determine either value.
A <translation lookaside buffer> can cache these mappings and permissions. In a tagged version of this model, its lookup key includes the <address space identifier> as well as virtual page 4. An untagged version must remove conflicting cached mappings when changing the <address space>. Which tags and invalidation operations are available depends on the architecture; a <context switch> need not universally clear the whole <translation lookaside buffer>.<Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others/Paging: Faster Translations (TLBs)>[Operating Systems: Three Easy Pieces, chapter 19, Paging: Faster Translations (TLBs), section 19.5, printed pp. 9–10: flushing and address-space identifiers]{ref}
The arithmetic explains the beauty of <paging>: a mapping can move an entire <memory page> without changing its internal positions. Indeed, for two offsets $d_1,d_2$ in the same mapped <memory page>,
$$
(fP+d_2)-(fP+d_1)=d_2-d_1.
$$
For process A, virtual page 4 spans `0x100`–`0x13F` and maps to `0x340`–`0x37F`. Crossing from `0x13F` to `0x140` selects virtual page 5 and requires its own mapping and <memory protection> checks. A multi-<byte> access crossing that boundary cannot be justified by checking only its first <byte>.
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