= Analog switch leakage current
{title2=$I_{\rm leak}$}
\b[Analog switch leakage current] is unwanted <electric current> at an <analog switch>'s signal terminals under stated terminal potentials, switch state and <temperature>. It can produce a steady offset in a resistive load or accumulate <electric charge> on an isolated <capacitor>. The manufacturer's equivalent circuits distinguish on-state and off-state leakage paths; their effects depend on the external circuit.<MT-088: Analog Switches and Multiplexers Basics>[p5, Figures6–7, DC errors in the on and off states]{ref}
For an original chosen model, let a constant $20\,\mathrm{pA}$ enter a node with a $50\,\mathrm{M\Omega}$ <resistor> to a reference. The steady <electric potential difference> error is $IR=1.0\,\mathrm{mV}$. Replacing that load by an initially isolated $200\,\mathrm{pF}$ <capacitor> instead gives
$$
\frac{dv}{dt}=\frac{I_{\rm leak}}C=0.10\,\mathrm{V\,s^{-1}}.
$$
A $100\,\mathrm{\mu V}$ drift allowance is exhausted in $1.0\,\mathrm{ms}$. This <leakage-limited hold time> assumes constant leakage and <capacitance>; it ceases to apply if the changing node potential substantially changes the leakage. With both the <resistor> and <capacitor> present, $C\,dv/dt=I_{\rm leak}-v/R$ approaches the steady error exponentially.
To measure the effect, hold the switch control fixed, disconnect the intended signal current and record the stored-node slope with known total <capacitance>. Repeat for relevant terminal potentials and <temperatures>. Readout input current and board leakage must be included in the <measurement model>. A one-time step at a control transition instead suggests <analog switch charge injection>; a sustained slope after that step is a different error mechanism.
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