= Binary multiplier
A digital circuit implementing <binary multiplication>. A <combinational logic> implementation forms shifted partial products with <AND gates> and combines them with <adders>. A <sequential circuit> can instead reuse one <adder>, storing a partial sum, a shifted multiplicand, and the remaining multiplier in <digital registers>. If those quantities are $P,M,Q$, the update $P\gets P+(Q_0?M:0)$, $M\gets2M$, $Q\gets\lfloor Q/2\rfloor$ preserves $P+MQ$. Starting with $(0,X,Y)$ and stopping when $Q=0$ therefore produces $P=XY$, provided widths prevent overflow.
Back to article page
