= Cache
{disambiguate=computing}
{wiki}
= Memory cache
{synonym}
A store of selected information kept for faster reuse. A <translation lookaside buffer> is a <memory cache> of <address translations>; a <buffer cache> instead holds device-block contents.
For a data <memory cache>, the useful bargain is to keep a small selection of <computer memory> close to the <CPU>. A <cache hit> serves a read from that selection; a <cache miss> requires obtaining the contents elsewhere. <Temporal locality> helps a retained <cache block> serve repeated reads, and <spatial locality> helps one transferred <cache line> serve neighbouring <bytes>. Placement, capacity and <LRU replacement> determine whether that opportunity survives until the next read. <Dive into Systems by Suzanne J. Matthews and others/11.4. CPU Caches>{ref}
The worked <memory access trace> below uses twelve single-<byte> reads at these decimal <physical addresses>, in this fixed order:
$$
0,4,32,0,16,32,4,48,52,0,16,0.
$$
Assume an initially empty <fully associative cache>, 16-<byte> aligned <cache blocks>, and capacity two <cache slots>: 32 <bytes> of cached data, excluding metadata. Use exact <LRU replacement>, refreshing recency on every read, including <cache hits>. Every <cache miss> fetches its requested <cache line> completely before the next read; only a full <memory cache> needs an eviction. There are no writes, fetching ahead of requests, external invalidations, or overlapping reads. All addresses denote ordinary cacheable <computer memory>, and <address translation> is outside this model. These are deliberately synthetic assumptions, not specifications of a particular <CPU>.
This makes the outcome reproducible from the <memory access trace>, rather than from an informal impression that data are “nearby” or “recent”. The <cache line> geometry below identifies the requested unit; <fully associative cache> enumerates the resulting states; <average memory access time> translates the counts into a simple timing calculation.
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