= Capacitor-stage quantization error
<Capacitor-stage quantization error> is the residual <reactive power> caused by choosing among discrete settings of a <capacitor bank> instead of a continuously adjustable correction. In a fixed sinusoidal operating model, let the load absorb $Q_L$ and let the target residual be $Q_t$. The desired capacitive correction is $q_*=Q_L-Q_t$. Selecting available correction $q$ leaves
$$
r=(Q_L-q)-Q_t=q_*-q.
$$
The error concerns the selected setting, separately from sensing error, changing load and component tolerance.
For equal stages of magnitude $q_s$ and an available range covering the desired correction, nearest-stage selection chooses an integer $k$ nearest $q_*/q_s$. Hence
$$
|r|=|q_*-kq_s|\le q_s/2.
$$
At a half-stage tie either neighbor attains the bound. A policy forbidding a negative residual relative to zero instead rounds downward and gives $0\le Q_L-kq_s<q_s$, away from the bank's capacity limits. The two policies solve different constrained problems.
For an original zero-target example, let $Q_L=640\,\mathrm{var}$ and $q_s=250\,\mathrm{var}$. Three stages give $r=-110\,\mathrm{var}$; two give $r=+140\,\mathrm{var}$. With <active power> $P=1000\,\mathrm W$, nearest-stage selection guarantees
$$
\mathrm{pf}\ge\frac{P}{\sqrt{P^2+(q_s/2)^2}}\approx0.9923,
$$
provided the zero-reactive target is within range and the sinusoidal fixed-load assumptions hold. At only $P=200\,\mathrm W$, the same worst-case bound falls to about $0.8480$. A stage size suitable at high demand need not give the same numerical <power factor> at low demand.
Unequal stages require the actual attainable set. Stages of 100 and 400 vars permit $\{0,100,400,500\}$ vars. At a desired 250 vars, the nearest setting leaves 150 vars error, despite the smallest stage being only 100 vars. The relevant bound is half the largest gap between neighboring attainable settings in the tested range, not half the smallest component. Outside the bank's range, clipping to an endpoint can leave a larger error.
At fixed <frequency>, a fixed <capacitance> gives $q_s=\omega C_sV^2$, so stage magnitudes also change with RMS <electric potential difference>. Eaton's paper describes discrete stage sizes, combinations and automatic control; the error bounds above are original consequences of that ideal setting model.<Capacitor Application Issues by Thomas M. Blooming and Daniel J. Carnovale>[Section V.C–D, printed p.6, stage sizes and fixed versus switched capacitors]{ref} A proposed test records the actual stage states and terminal quantities while slowly varying a known load across thresholds. Compare the observed residual with the attainable-setting prediction before assigning every deviation to quantization.
Back to article page
