Clock-to-Q delay
= Clock-to-Q delay
{title2=$t_{\mathrm{CQ}}$}
The time from a triggering <clock edge> to the corresponding settled output of a <flip-flop>, under specified loading. The time available between successive active <clock edges> must accommodate this delay, the <combinational critical path>, the receiving <flip-flop>'s <setup time>, and any clock uncertainty.