CMOS NAND gate
= CMOS NAND gate
{c}
A static <CMOS> implementation of a <NAND gate> has a <pull-down network> of <NMOS transistors> in series and a <pull-up network> of <PMOS transistors> in parallel. With $k$ inputs it uses $k$ devices of each kind. All inputs high connect the output to ground; any low input breaks the pull-down path and connects the output to the positive supply through its corresponding p-channel device.