= Dead time
{disambiguate=power electronics}
{title2=$t_d$}
= Bridge switching dead time
{synonym}
<Bridge switching dead time> is an intentional nonoverlap interval between complementary conduction commands in a power-switching leg. It allows the outgoing device to cease conducting before the incoming device conducts, reducing <H-bridge shoot-through>. The applicable interval depends on propagation and device switching delays, not only on the timestamps of ideal logic commands. Nexperia's primary bridge discussion introduces the delay between turning off one pair and turning on the other, while retaining a path for inductive current.<Using power MOSFETs in DC motor control applications by Nexperia>[§4.1, Modes of switching, Figures 5–6]{ref}
For an original timing bound, command the outgoing device off at $t=0$ and the incoming device on at $t=t_d$. Let $\tau_{\rm off,max}$ be the latest possible end of outgoing conduction, and $\tau_{\rm on,min}$ the earliest incoming conduction delay after its own command. A sufficient nonoverlap condition in this delay model is
$$
t_d+\tau_{\rm on,min}\ge\tau_{\rm off,max}.
$$
With an additional positive timing margin $m$, choose
$$
t_d\ge\max\left(0,\tau_{\rm off,max}-\tau_{\rm on,min}+m\right).
$$
The two switching directions can require different bounds. The inputs must cover the operating conditions for which the guarantee is claimed.
Suppose the latest turn-off completion is $80\,\mathrm{ns}$ and the earliest turn-on delay is $20\,\mathrm{ns}$. Zero modeled overlap requires at least $60\,\mathrm{ns}$ of commanded separation; a stipulated $20\,\mathrm{ns}$ extra margin gives $t_d=80\,\mathrm{ns}$. Incoming conduction then starts no earlier than $100\,\mathrm{ns}$, leaving at least $20\,\mathrm{ns}$ after the outgoing device has ceased. These numbers illustrate the bound rather than a particular gate-driver specification.
Longer separation also changes the output waveform. In an original half-bridge example with rails 0 and $V_d$, suppose one nominal high interval per period is shortened by exactly $t_d$, with the removed interval clamped to the low rail. The mean <electric potential difference> changes by
$$
\Delta\overline v=-V_d\frac{t_d}{T}.
$$
For $V_d=24\,\mathrm V$, $T=50\,\mathrm{\mu s}$ and $t_d=100\,\mathrm{ns}$, this is $-48\,\mathrm{mV}$. The <dead-time output-voltage error> in a complete bridge depends on which intervals are replaced and on load-current direction; this one-pulse calculation does not supply a universal coefficient.
During nonoverlap, the <electric current> of an <inductor> cannot disappear instantly. Its path can pass through <diodes> or other permitted conducting devices, and the midpoint potential depends on that path. A proposed test records both actual transition timing and the resulting terminal waveform under the intended load conditions. It tests the timing margin and output distortion separately, instead of treating an increased programmed delay as a complete characterization.
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