= Gate-normalized detector output
{title2=$\bar v_g$}
A \b[gate-normalized detector output] reports an integrated detector signal divided by the duration of the <detection time gate>. For an input <electric potential difference> waveform $v(t)$ and a gate from $t_0$ to $t_0+T_g$, the input-referred average is
$$
\bar v_g=\frac1{T_g}\int_{t_0}^{t_0+T_g}v(t)\,dt.
$$
Its units are those of <electric potential difference>, whereas the integral has units of <electric potential difference> times time. The SR250 gated integrator implements integration followed by gate-width normalization and an adjustable amplification stage.<SR250 Gated Integrator by Stanford Research Systems>[PDFp1, Overview and Signal Inputs]{ref}
For an original idealized detector pulse, take $v(t)=2\,\mathrm{mV}$ from0 to4nanoseconds and zero outside that interval. A gate covering0–4nanoseconds integrates $8\,\mathrm{mV\,ns}$ and reports an average of2millivolts. A gate covering0–8nanoseconds integrates the same area but reports1millivolt. Thus unchanged admitted pulse area need not give an unchanged normalized output.
The gate average also differs from the average over a full repetition period. For the same pulse repeated once per microsecond, the full-period mean is only8microvolts. Comparing instruments therefore requires knowing whether the reported quantity is pulse area, within-gate average or full-period average.
A constant baseline $b$ contributes
$$
\frac1{T_g}\int_{t_0}^{t_0+T_g}b\,dt=b.
$$
Gate-width normalization does not remove that baseline. A separate reference or subtraction measurement is needed to distinguish it from the desired signal.
An apparatus check overlays the gate monitor and detector waveform on an <oscilloscope>, then varies the gate width while keeping its start fixed. A flat plateau should retain its input-referred average while the gate remains inside it; a short pulse diluted by additional quiet time behaves like the example above. <Gate timing jitter> and <gate-width jitter> can alter which signal portion is admitted and which duration is used for normalization.<SR250 Gated Integrator by Stanford Research Systems>[PDFp2, Gate Timing and Additional Outputs]{ref}
Back to article page
