Half adder
= Half adder
{title2=$a+b=s+2c$}
A <combinational logic> circuit adding two input <bits> $a,b$ to a sum <bit> $s=a\oplus b$ and <carry> <bit> $c=a\land b$. An <exclusive or> gate and an <AND gate> implement it. The identity $a+b=(a\oplus b)+2(a\land b)$ follows by checking the four input pairs. A <half adder> has no input carry, so adding three equally weighted <bits> needs a different circuit or multiple stages.