= Integrator reset dead time
{title2=$T_{\rm dead}$}
\b[Integrator reset dead time] is the interval during which incoming charge is excluded from the reported measurement because the integrator is resetting or not yet ready for acquisition. A switched-integrator implementation has distinct integration, hold and reset states; the historical datasheet shows those states and their timing.<ACF2101 Low Noise, Dual Switched Integrator datasheet>[p9, Modes of Operation and Hold and Reset Switches, Figures3–4]{ref}
For an original periodic schedule, acquire during the first $80\,\mathrm{\mu s}$ of every $100\,\mathrm{\mu s}$ cycle, reset for the next $10\,\mathrm{\mu s}$ and exclude the final $10\,\mathrm{\mu s}$ for settling. The <duty cycle> is $80\%$. If short-pulse arrival phases are independent and uniform over that cycle, the expected captured fraction is $0.80$.
That fraction does not apply to every pulse train. Pulses spaced by $100\,\mathrm{\mu s}$ and arriving at phase $85\,\mathrm{\mu s}$ are all missed in the ideal schedule. The same train at phase $20\,\mathrm{\mu s}$ is entirely captured. The clock synchronization matters as much as the fraction of time spent acquiring.
A bench check compares accepted events with an independent pulse monitor while changing their phase relative to the reset command. State whether the excluded interval includes the switch delay, discharge interval, post-opening transient and readout recovery. A stable zero-input baseline alone cannot demonstrate that every pulse was accepted. The <integrator reset settling time> and a <reset charge-injection pedestal> concern readiness and initial conditions, while dead time concerns which signal arrivals contribute at all.
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