= JK flip-flop
{c}
= J-K flip-flop
{c}
{synonym}
At the active <clock edge>, the next state is $Q^+=J\neg Q\lor\neg K Q$: inputs $00$ hold, $01$ reset, $10$ set, and $11$ toggle. In particular, $K=0$ gives $Q^+=J\lor Q$, whereas $J=K=1$ gives $Q^+=\neg Q$. The standard function table is illustrated by a positive-edge device in the <CD4027B CMOS Dual J-K Flip Flop datasheet by Texas Instruments>[Section 8.2, p. 9]{ref}. Its asynchronous reset is active high; another circuit may specify an active-low clear.
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