= Memory management unit
{title2=MMU}
{wiki}
The hardware that performs <address translation> and access checks. Whether a <TLB miss> is resolved entirely by hardware or with <operating system> assistance depends on the architecture.
For <paging>, the <memory management unit> uses the active <address space> and the kind of access: reading, writing, or fetching an instruction. <Processor privilege level> can also affect permission. A <TLB hit> supplies cached translation attributes; it does not bypass <memory protection>. On a <TLB miss>, some architectures perform a hardware <page table walk>, while others enter an <operating system> refill handler. Both can resolve a resident mapping without a nonresident <page fault>.<Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others/Paging: Faster Translations (TLBs)>[Operating Systems: Three Easy Pieces, chapter 19, Paging: Faster Translations (TLBs), sections 19.1, 19.3–19.4, printed pp. 2, 6, 8: permission checks, refill ownership, and cached attributes]{ref}
\Image[/address-translation-tlb-control-path.png]
{title=Logical <address translation> control path: a cached mapping, refill, permission check, and separate data read}
This diagram is a logical dependency model for the toy single-<byte> read, rather than a timing diagram for a particular <CPU>. A <translation lookaside buffer> caches translations and access attributes; a data <memory cache> caches contents. A <TLB hit> can accompany a data <cache miss>, and a <TLB miss> can accompany a data <cache hit> after successful refill. Reading <page table entries> during refill is also distinct from reading the requested data. Actual implementations may overlap steps.
Extend process A's toy <address space> with these independent starting states. Virtual page 4 is resident in <page frame> 13 and readable but not writable. Virtual page 5 is a permitted readable <memory page> whose old contents are in backing storage and which is initially nonresident. Virtual page 6 has no mapping authorized by the <operating system>. Assume permission changes and eviction always invalidate affected cached translations before later accesses, no <copy-on-write> policy, and a free <page frame> 2 for loading virtual page 5.
* Read `0x12D` with an empty <translation lookaside buffer>: a <TLB miss> discovers resident virtual page 4, caches its attributes, and reads <physical address> `0x36D`. There is no nonresident <page fault>.
* Write `0x12D` with that translation already cached: a <TLB hit> finds the mapping, but <memory protection> denies the write. The target <byte> remains unchanged even though its <page frame> is resident.
* Read `0x16D`: virtual page 5 and offset 45 are permitted but nonresident. A <page fault> lets the <operating system> load the contents into <page frame> 2, update the <page table>, and retry. Successful <address translation> then gives $2\cdot64+45=173=\mathtt{0x0AD}$; the requested read occurs only after the contents are ready.
* Read `0x1AD`: virtual page 6 and offset 45 have no authorized mapping. The <operating system> rejects the access in this model; finding a free <page frame> would not supply authorization.
\Image[/memory-access-permission-residency-traces.png]
{title=Four original access traces distinguish <TLB misses>, denied writes, nonresident <memory pages>, and unauthorized addresses}
A nonresident <memory page> and a forbidden access therefore require different decisions: supplying contents can repair the former, while the latter needs authorization. Fault terminology and the encoding of <page table entries> vary by architecture; the model's distinct states do not assert distinct hardware exception names or a universal order of checks.<Operating Systems: Three Easy Pieces by Remzi H. Arpaci-Dusseau and others/Beyond Physical Memory: Mechanisms>[Operating Systems: Three Easy Pieces, chapter 21, Beyond Physical Memory: Mechanisms, sections 21.2–21.5, printed pp. 3–7, especially the terminology aside and Figures 21.2–21.3]{ref}
The separation makes <virtual memory> useful: ordinary accesses can reuse cached mappings while the <operating system> intervenes when policy or residency requires work. It also makes failures easier to diagnose. A lost cached translation, unavailable contents, and denied permission are three different obstacles, even when all interrupt the same requested read.
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