= Microarchitecture
A <microarchitecture> is a particular hardware organization implementing an <instruction set architecture>. It specifies mechanisms such as <machine instruction>[instruction] decoding, execution units, <instruction pipelining>[pipelines], <memory caches>[caches] and <branch prediction>. Two processors can expose the same instruction-set contract while making different choices about those mechanisms.
For example, both processors may correctly execute a load followed by an integer addition. One can overlap independent <machine instructions>[instructions] and obtain the load from a nearby <memory cache>[cache], while the other waits for a longer memory access. The architectural result agrees, but cycle counts differ. Speculative work must be discarded or committed in a way that preserves the required visible behavior. This distinction explains why compatibility with one <machine instruction>[instruction] set does not imply equal performance, power consumption or physical implementation.<Instruction Set Architecture in the Arm documentation>[ISA versus microarchitecture]{ref}
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