= Solution
<Register forwarding> supplies a later instruction with a computed value before that value has reached the <register file>. It removes some <read-after-write hazards> without changing the program's meaning. Consider these symbolic <machine instructions>, with the destination first:
``
ADD r1, r2, r3
SUB r4, r1, r5
``
In the five-stage <in-order pipeline>, the addition produces its result at the end of EX. In the next cycle the subtraction is in EX, although the addition has not yet reached WB. A bypass from the addition's EX/MEM <pipeline register> to the subtraction's <arithmetic logic unit> input supplies the new `r1`; the old value read in ID must be overridden.
The bypass control compares source and destination <processor register> identifiers and selects the youngest applicable older producer. It must also check that the producer actually writes that <processor register>. \b[Forward the newest available result instead of waiting for its writeback.] A <load instruction> is different: its value is normally available only at the end of MEM, so an immediately following dependent instruction still needs a <pipeline stall> in this five-stage arrangement.
$$
\boxed{\text{Forward the newest ready result directly to its dependent instruction.}}
$$
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