= Solution
<Cache prefetching> moves a <cache line> towards the <CPU> before a demand access needs it. A correctly timed request overlaps the <cache miss penalty> with earlier computation, so a subsequent <load instruction> can find a <cache hit> instead of stopping the <in-order pipeline> in MEM. Requests directed at several levels of a <cache hierarchy> can prepare nearby data in a small fast <memory cache> while staging more distant future data in larger levels. The separate request <computer bus> avoids making those address requests compete directly with returning data; returned <cache lines> still consume transfer capacity.
For a <store instruction>, the gain depends on the write policy. With a <write-allocate cache>, fetching its target <cache line> early can avoid the allocation <cache miss> and help the <store buffer> drain. On a <multicore processor>, a write-oriented prefetch may additionally obtain <cache coherence> ownership; an ordinary read prefetch alone does not guarantee write permission. A <store buffer> can already hide an individual write's <latency>, so the visible gain may appear only when it would otherwise fill. With a <no-write-allocate cache>, fetching the <cache line> just to overwrite it can be unnecessary. \b[Loads benefit directly from earlier data arrival; stores benefit when prefetching removes a required allocation or ownership delay.]
$$
\boxed{\text{Overlap cache filling with work before a demand access.}}
$$
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