= Solution
In IF, fetch `PREFETCH` normally. In ID, recognize its opcode, read the base <processor register> and immediate offset, and set controls selecting a prefetch request rather than a <load instruction> or <store instruction>. Ordinary <register forwarding> and <data hazard> interlocks still apply to that base <processor register>. In EX, use the <arithmetic logic unit> to form the effective <memory address>.
Latch that <memory address> and a prefetch-valid control into EX/MEM. In MEM, put the <memory address> and any hint information on the dedicated request <computer bus>, or enqueue them in a small prefetch-request queue. The <cache prefetching> engine handles lookup, allocation and the later <cache line> return independently. Do not wait for the fill or select the returned data as a <register file> input. In WB, disable architectural <processor register> and <processor condition flag> writes; the instruction simply leaves the <in-order pipeline>.
If the request path is busy, dropping the hint is compatible with the contract in part (ii), and preserves its nonblocking purpose. A design that instead stalls until queue space exists can still be correct but reduces the performance benefit. A <memory management unit> must not turn a speculative hint into an ordinary protection fault: discard an invalid target, or use an appropriately checked nonfaulting translation path. Suppress device transactions for <memory-mapped input-output> and avoid speculative writes. \b[Use the existing address-generation datapath, add a prefetch request/control path, and disable demand-load waiting and writeback.]
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\boxed{\text{EX forms the address; MEM queues the hint; WB writes nothing.}}
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