= Solution
Consider a slow <load instruction> controlling one conditional addition, followed by independent work. The following is schematic A32 <assembly language>; the plain `ADD` and `MUL` forms shown do not update <processor condition flags>:
``
LDR r0, [r1]
CMP r0, #0
BNE skip
ADD r2, r2, #1
skip:
MUL r8, r9, r10
``
Without <branch prediction>, the unresolved conditional branch prevents fetching beyond it until the <load instruction>, comparison and branch resolution complete. The multiplication does not depend on `r0`, yet the <out-of-order execution> machinery cannot execute it if it has not been fetched and issued.
<Conditional execution> removes that branch:
``
LDR r0, [r1]
CMP r0, #0
ADDEQ r2, r2, #1
MUL r8, r9, r10
``
`ADDEQ` adds one exactly when the <zero flag> from `CMP` is set; otherwise it preserves `r2`. The instruction stream has a known sequential continuation, so the <CPU> can fetch and issue the multiplication while the <load instruction> is outstanding. With available <reservation stations> and a free multiplier, independent multiplication overlaps the <load instruction>'s <latency>.
\b[Predication removes a control-flow obstacle to finding independent work; it does not resolve the slow load or its dependent condition earlier.] The conditional addition must still select the correct result after the <processor condition flags> become known. The gain is especially useful for a short conditional region, since instructions whose predicates are false still occupy fetch and issue resources. On a strictly blocking <in-order pipeline>, a slow demand <load instruction> would still stop later work in MEM; the overlap here uses the question's <out-of-order execution> setting and a nonblocking memory path.
$$
\boxed{\text{Predication exposes independent later work while the condition waits.}}
$$
Back to article page
