= Solution
Use two different shared locations `x` and `y`, initially zero, and two <CPU cores>. The following are architectural memory operations, with each result kept in its own <processor register>:
|| Core 0
|| Core 1
| `STORE [x], 1`
| `STORE [y], 1`
| `LOAD r0, [y]`
| `LOAD r1, [x]`
Each <CPU core> can retire its write into its own <store buffer>. Before either write drains, Core 0's <load instruction> misses its own <store buffer> because it asks for `y`, while Core 1's asks for `x`. Both can read the old shared values. Afterwards the buffers drain and both locations become one. Thus
$$
\boxed{r_0=r_1=0\quad\text{is possible with separate store buffers}.}
$$
There is no contradiction with <cache coherence>: each location still has an agreed write order. The unusual observation concerns ordering across two different locations. This is the standard store-buffering example, also permitted by <total store order>.<Understanding POWER Multiprocessors (2011)>[§2.1, “SB: Store Buffering”, printed p. 2]{ref}
On a single <CPU core> executing the two logical participants in an ordinary <thread interleaving>, the same pair of zero observations is impossible under the usual shared-buffer and own-write-forwarding behavior. To read `y=0`, Core-0's logical read must precede the other participant's write of `y`; to read `x=0`, the other read must precede the write of `x`. Combining these requirements with each participant's program order gives the impossible cycle
$$
W_x<R_y<W_y<R_x<W_x.
$$
If a write is still buffered across a context switch on that single <CPU core>, a later read of the same address sees it through <store-to-load forwarding> rather than returning an older value. Hence separate <store buffers> on different <CPU cores> enable the observation; the comparison assumes ordinary coherent cacheable <computer memory> and no device accesses or additional writes. \b[A locally completed store need not yet be visible to another core.]
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