= Solution
Compute the parity into the second wire, phase that wire with the <T gate>, then uncompute with the same <controlled-NOT gate>. The answer is
$$
\boxed{G=\mathrm{CNOT}\,(I\otimes T)\,\mathrm{CNOT}.}
$$
For computational bits $x,y$, the successive states are $|x,y\rangle\mapsto|x,x\oplus y\rangle\mapsto e^{i\pi(x\oplus y)/4}|x,x\oplus y\rangle\mapsto e^{i\pi(x\oplus y)/4}|x,y\rangle$. The parity $x\oplus y$ is one precisely on the two odd-parity inputs. Thus, in the ordered <computational basis> $00,01,10,11$, the <matrix> is exactly $\operatorname{diag}(1,e^{i\pi/4},e^{i\pi/4},1)$, with no omitted overall phase. This is a <two-qubit parity phase gate>.
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