= Solution
The processor selects the device's data or control register by presenting its address, either in memory-mapped input-output space or in a distinct port-address space. For a write, it places data on the <computer bus> and asserts the appropriate write control. For a read, it asserts read control and samples the data supplied by the addressed device. The device recognizes the address and uses the bus timing or acknowledge protocol to indicate completion, including wait states if needed.
The processor uses status registers to determine readiness and control registers to request operations. This register-level communication can be arranged using <polled input-output> or <interrupt-driven input-output>; the bus transaction itself and the policy for waiting on a device are separate issues.
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