= Solution
The left transistor is an n-channel <MOSFET> in a p-type <silicon> substrate; the right is a p-channel <MOSFET> in an n-well. The region assignments are:
* \b[a:] n-well, <silicon> doped with a donor such as <phosphorus>.
* \b[b:] p+ substrate contact, heavily boron-doped <silicon>.
* \b[c:] n+ source of the nMOS device, arsenic- or phosphorus-doped <silicon>.
* \b[d:] n+ drain of the nMOS device, with the same donor dopants.
* \b[e:] p+ drain of the pMOS device, boron-doped <silicon>.
* \b[f:] p+ source of the pMOS device, boron-doped <silicon>.
* \b[g:] n+ well contact, heavily donor-doped <silicon>.
* \b[h:] nMOS gate, conventionally heavily doped polycrystalline <silicon> in this process.
* \b[i:] thin nMOS gate dielectric, conventionally <silicon dioxide>.
* \b[j:] pMOS gate, conventionally heavily doped polycrystalline <silicon>.
* \b[k:] thin pMOS gate dielectric, conventionally <silicon dioxide>.
The diagram additionally labels the conductor \b[l], although the requested range ends at k: it is a metal contact/interconnect, conventionally aluminium or an aluminium alloy in an older planar process. Modern processes can use metal gates, high-permittivity gate dielectrics and different interconnect stacks; these are alternatives, not evidence that the illustrated conventional gate is aluminium.
For a <CMOS inverter>, join h and j to the input and d and e to the output. Connect f and g to $V_{\rm DD}$, and b and c to ground; these ties keep the body junctions appropriately biased.
\Image[/past-exam-of-the-mphil-in-micro-and-nanotechnology-enterprise-course-of-the-university-of-cambridge/2020/paper-1-cmos-inverter.png]
{title=Complementary transistor connections, with each body tied to its supply rail}
{source=paper-1-cmos-inverter.py}
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