= Solution
Clean the exposed <silicon> and grow a thin, high-quality \b[SiO2 gate dielectric by controlled dry thermal <oxidation>]. Deposit polycrystalline <silicon>, conventionally by low-pressure <chemical vapour deposition> from silane, dope it in situ or by subsequent implantation and activation, and pattern/etch it to define the two gates. <Phosphorus> or <arsenic> gives n+ polysilicon; <boron> gives p+ polysilicon where the selected gate-work-function process requires it. A traditional single-poly process may use a common gate doping instead; gate and source/drain doping need not be identical.
The patterned gates subsequently serve as self-alignment masks for donor-doped nMOS source/drain and acceptor-doped pMOS source/drain regions. Annealing activates these dopants. Keep the oxide thin and uniform enough for strong electrostatic control but free from pinholes and excessive leakage. A high-permittivity dielectric deposited by <atomic layer deposition> with a metal gate is a modern alternative, rather than the conventional polysilicon/SiO2 stack drawn.
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