= Solution
A <junction field-effect transistor> has a conducting channel between source and drain, with gate regions forming reverse-biased <p-n junctions> to that channel. In an n-channel device, a more negative gate-source <electric potential difference> increases the <reverse bias> and widens the <depletion region>. The conducting cross-section shrinks, reducing the drain <electric current>. The gate ideally draws only a small leakage <electric current>, giving a high input resistance; the source-drain supply provides the controlled output <power>. Carrier motion in a p-channel device reverses the relevant polarities.
At small positive $V_{DS}$, the channel conducts approximately as a resistor. As the potential rises from source to drain, the local gate-channel <reverse bias> increases toward the drain. The depletion layers are therefore thicker there. For a symmetric n channel of half-thickness $a$, uniformly doped at density $N_D$, the one-sided <depletion approximation> gives
$$
w(y)\simeq\sqrt{\frac{2\varepsilon_s}{eN_D}\left[V_{\rm bi}+V(y)-V_{GS}\right]},
$$
where $w$ is the depletion width from each side and $V_{\rm bi}$ the built-in junction potential. The neutral channel closes locally when $w=a$. Define the positive geometrical depletion <electric potential difference> $U_P=eN_Da^2/(2\varepsilon_s)$. The approximate drain-end pinch-off condition is
$$
\boxed{V_{DS,\rm sat}\simeq U_P-V_{\rm bi}+V_{GS}.}
$$
More negative gate bias makes this saturation occur at a smaller drain <electric potential difference>.
\Image[/past-exam-of-the-quantum-condensed-matter-course-of-the-university-of-cambridge/2016-jfet-pinch-off.png]
{title=Gate depletion, drain-end pinch-off and approximate current saturation in an n-channel JFET}
<Pinch-off in a junction field-effect transistor> does \b[not] mean that the drain <electric current> vanishes. <Electrons> arriving through the remaining neutral channel are swept across the high-field depleted region into the drain. Further increases in $V_{DS}$ mostly fall across that region, so the <electric current> changes only weakly: this is the saturation regime used for amplification. Channel shortening gives a finite output slope in real devices. Excessive reverse <electric potential difference> eventually causes breakdown, beyond the normal saturation model.
A sufficiently negative gate <electric potential difference> can instead deplete the entire channel from the source end and produce \b[cutoff]. In the simplified geometry its threshold is $V_{GS,\rm off}\simeq V_{\rm bi}-U_P<0$. A commonly used approximate transfer law in saturation is
$$
I_D\simeq I_{DSS}\left(1-\frac{V_{GS}}{V_{GS,\rm off}}\right)^2,\qquad V_{GS,\rm off}\leq V_{GS}\leq0.
$$
Here $I_{DSS}$ is the saturated drain <electric current> at zero gate-source bias. The square law is a useful device approximation, not an exact result for arbitrary channel profiles. It connects field control of depletion to a measurable transfer characteristic while keeping drain-end pinch-off distinct from complete gate cutoff.
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