= Solution
A <D flip-flop> stores one <bit>. On each active <clock edge>, it samples the input D and changes its stored output Q to that sampled value after the propagation delay. Between active edges, it holds the value. In the ideal discrete model,
$$
\boxed{Q_{k+1}=D_k,}
$$
where $D_k$ is the input sampled at edge $k$ and $Q_{k+1}$ is the state just after that edge. This assumes D meets the required <setup time> and <hold time>; asynchronous set or reset inputs, if present, are inactive.
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