= Solution
A fully <synchronous sequential circuit> has all its state stored in edge-triggered elements driven by a common <clock signal>, with combinational logic computing the next state from the current state and inputs. State updates occur together at the designated <clock edges>, rather than letting one register output serve as another register's ripple clock. Its ideal equations are
$$
\boxed{s_{k+1}=F(s_k,u_k),\qquad z_k=G(s_k,u_k).}
$$
For a <Moore machine> the output <function> depends only on the state, $z_k=G(s_k)$. Physical design must leave enough time for register-to-register combinational paths and satisfy <setup time> and <hold time> at every receiving storage element.
Back to article page
