= Solution
A particularly transparent design uses six <D flip-flops> in a <one-hot encoding>. Let $Q_i=1$ mean that face $i$ is displayed. Initialize $Q_1=1$ and $Q_2=\cdots=Q_6=0$, and wire the next-state inputs as a ring:
$$
\boxed{D_1=Q_6,\quad D_2=Q_1,\quad D_3=Q_2,\quad
D_4=Q_3,\quad D_5=Q_4,\quad D_6=Q_5.}
$$
All six <D flip-flops> share the same active <clock edge>. Each pulse moves the single stored $1$ to the next position, giving the <state-transition diagram> cycle $1\to2\to3\to4\to5\to6\to1$. The <representation invariant> “exactly one $Q_i$ is high” holds after initialization and is preserved by rotation. Six <D flip-flops> are more than the three-<bit> theoretical minimum, but their simple wiring gives a complete implementation without requiring that minimum.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2005/computing-prelims-2005-dice-ring.png]
{title=One-hot ring state register and the six lamp patterns, including the original opposite diagonals on faces 2 and 3}
Decode the seven lamps by their positions, with $T,M,B$ denoting top, middle and bottom, and $L,R$ denoting left and right. Let $L_C$ be the center lamp. In the original figure, face 2 uses top-left and bottom-right, while face 3 uses top-right and bottom-left plus center; the two diagonals must therefore have different controls.<Functional programming, data structures and algorithms, procedural programming, and digital hardware examination paper by the University of Oxford (2005)>[Printed p. 6, Figure 1(b), faces 2 and 3]{ref} The required <OR gate> decoder is
$$
\boxed{\begin{aligned}
L_{TL}=L_{BR}&=Q_2\lor Q_4\lor Q_5\lor Q_6,\\
L_{TR}=L_{BL}&=Q_3\lor Q_4\lor Q_5\lor Q_6,\\
L_{ML}=L_{MR}&=Q_6,\\
L_C&=Q_1\lor Q_3\lor Q_5.
\end{aligned}}
$$
For example, only the center is high in state $Q_1$, the first diagonal is high in state $Q_2$, and in state $Q_6$ both outer columns are high while the center is low. This verifies all six layouts directly.
To implement the switch behavior, use a rapid common <clock signal> and a sampled enable $S$, high while the switch is pressed. Each next-state input is then selected between its advancing value and its own stored value:
$$
\boxed{D_i=(S\land Q_{\mathrm{prev}(i)})\lor
(\overline S\land Q_i),\qquad
\mathrm{prev}(1)=6,\quad\mathrm{prev}(i)=i-1\ (i>1).}
$$
One <multiplexer> per <D flip-flop> implements that selection. While enabled the <electronic dice> advances; otherwise every <D flip-flop> reloads its own value and the display holds. The enable supplied to this synchronous design must be stable at sampling edges. A reset or preset facility must establish the specified one-hot initial state: an all-zero ring does not start itself.
With a rapid <clock signal>, uncertainty in human release timing makes the final face practically unpredictable. The <sequential circuit> itself is deterministic; this observation alone is not a proof that its six outcomes have equal probabilities.
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