= Solution
A <serial-in parallel-out shift register> is a chain of <digital registers> driven by the same <clock signal>. At each active <clock edge>, the first stage captures the input and every later stage captures the preceding stage's old value. Its parallel outputs expose the successive delayed samples simultaneously.
Let $a_n$ be the current sample and, immediately before its sampling edge, let $h_1=a_{n-1},\ldots,h_{k-1}=a_{n-k+1}$. Feed these signals to <combinational logic> implementing $f$. Then
$$
\boxed{z_n=f(a_n,h_1,\ldots,h_{k-1})=f(a_n,a_{n-1},\ldots,a_{n-k+1}).}
$$
Only $k-1$ stored history stages are needed if the current input is used directly. Alternatively, a $k$-stage <shift register> exposes all $k$ samples after the edge. A separate output <digital register> can capture the first arrangement at the edge, giving a fully sampled output. Initialize the history, or regard the first $k-1$ cycles as a filling interval.
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