= Solution
The <opcode> occupies bits $31:26$, the <arithmetic logic unit> operation is wired directly to $15:10$, and an <immediate operand> uses all of $9:0$. A three-register instruction needs fifteen register-selection <bits>, whereas an immediate instruction must retain independent source and destination selectors outside $9:0$.
Thus put $r_s$ and $r_d$ in the ten bits $25:16$, and place $r_t$ in five of $9:0$, where it can overlap the unused <immediate operand> of a register instruction. One valid <instruction encoding> is
$$
\boxed{r_s=I[25:21],\qquad r_d=I[20:16],\qquad r_t=I[9:5].}
$$
Bits $4:0$ are unused for a three-register instruction. In an immediate instruction, $r_t$ has no effect because its read value is deselected by the `ToAlu` <multiplexer>. In a `store`, $r_s$ selects the address and $r_t$ selects the data; $r_d$ must be zero to suppress the incidental register write. These observations follow the original <datapath>, particularly its direct $val_s$ memory-address connection and the connection from the `ToAlu` output to memory write data.<Digital systems, linear algebra, introduction to formal proof examination paper by the University of Oxford (2013)>[Printed p. 3, processor block diagram]{ref}
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