= Solution
The `addi` <immediate operand> is a <byte-lane immediate>: an unsigned eight-bit quantity shifted by $0,8,16$ or $24$ positions. Thus
$$
\boxed{E(x)=b2^{8j},\qquad 0\leq b\leq255,\quad 0\leq j\leq3.}
$$
It is not the <sign extension> of a 16-bit constant used by the <MIPS instruction> `addi`. For example, this design can add $\mathtt{0x12000000}$ directly, but cannot add $\mathtt{0x00000123}$ in a single immediate instruction. A field containing byte $\mathtt{FF}$ in the low lane adds 255, not $-1$.
The `load` and `store` memory address is exactly the content of $r_s$. The <arithmetic logic unit> result is not connected to the memory-address input. Therefore
$$
\boxed{\text{native address}=R_s,\qquad\text{MIPS address}=R_s+\operatorname{signextend}_{16}(\text{offset}).}
$$
There is no native base-plus-offset calculation during either memory instruction. The paper does not specify exception behavior for signed overflow, so the representable constants and address calculation are the justified differences; the <datapath> alone cannot establish MIPS-compatible overflow traps.
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