= Solution
Let the stored <bits> be $G,H$, with $G$ most significant. The required <Gray code> transitions give
$$
00\to01\to11\to10\to00,\qquad\boxed{D_G=H,\qquad D_H=\overline G.}
$$
Connect $H$ directly to the first <D flip-flop>'s data input and feed $G$ through one <NOT gate> to the second input. Drive both enable inputs with $E$ and both clock inputs with the same clock. Thus $E=0$ holds both stored <bits>; $E=1$ takes the next <Gray-code counter> state at the active <clock edge>. Reset initializes $GH=00$.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2014/digital-systems-2014-counters.png]
{title=Enabled <Gray-code counter> and synchronous SOS sequencer: all stored <bits> share one clock}
With ordinary uncomplemented $Q$ outputs, one <NOT gate> is minimal: wiring alone cannot produce $\overline G$. If a <D flip-flop> already provides a complementary output, that output supplies the inversion without an external <logic gate>. This is a <Moore machine> because its output $GH$ depends only on stored state; $E$ controls transitions.
Back to article page
