= Solution
Use a <synchronous counter cascade>, with the three-<bit> <modulo-six counter> advancing on every active <clock edge> and the <Gray-code counter> advancing only when the old binary state is $101$. Its enable can therefore be
$$
\boxed{E=A C.}
$$
On the six valid binary states, $AC=1$ only at $101$. Both <digital counters> sample the same clock: at an edge leaving $101$, the binary output becomes $000$ and $GH$ simultaneously advances to the next <Gray code>. At all other edges $GH$ holds. Starting from $GHABC=00000$, this gives exactly the listed 24-state sequence. Use the shared clock and an enable, rather than making a combinational terminal-state signal into a new clock.<Digital systems, linear algebra, introduction to formal proof examination paper by the University of Oxford (2014)>[Question 3(c), printed page 4: original 24-row state/output table]{ref}
For the output $Y$, every state with $C=1$ has $Y=1$. For $C=0$, the only extra high states are $GH=01$ with binary state $010$, and $GH=11$ with binary state $000$ or $100$. On valid states these conditions are $H\overline G B$ and $HG\overline B$, respectively. Hence
$$
\boxed{Y=C+H\overline G B+HG\overline B=C\lor\bigl(H\land(G\mathbin{\oplus}B)\bigr).}
$$
The lower circuit in the figure implements this with an AND for $E$, an <exclusive or> on $G,B$, an AND with $H$, and an OR with $C$. The resulting <Morse code> output blocks, in <Gray code> order $00,01,11,10$, are
$$
010101\quad011101\quad110111\quad010101.
$$
Across the two middle blocks these join to three three-clock highs separated by one-clock lows; the first and last blocks provide the three single-clock highs of each S. The specified table is a repeating SOS symbol pattern; its wraparound has a one-clock low, rather than an added inter-message pause. The output is a <Moore machine> decoding of current stored <bits>; its value changes after those <bits> settle.
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