= Solution
A more economical static <CMOS> design follows from factoring the condition for $z=0$. The output is low exactly when both input pairs disagree:
$$
\neg z=(a\oplus c)\land(b\oplus d)
=(a\neg c\lor\neg a c)(b\neg d\lor\neg b d).
$$
Generate $\neg a,\neg b,\neg c,\neg d$ with four <CMOS inverters>. Write $n(x)$ or $p(x)$ for an <NMOS transistor> or <PMOS transistor> whose gate receives $x$. In the following network expressions, a dash means a series connection and $\parallel$ means a parallel connection.
Connect this eight-device <pull-down network> between $z$ and ground:
$$
\boxed{
\bigl[(n(a)-n(\neg c))\parallel(n(\neg a)-n(c))\bigr]
-\bigl[(n(b)-n(\neg d))\parallel(n(\neg b)-n(d))\bigr].}
$$
The first parallel module conducts exactly when $a\ne c$ and the second exactly when $b\ne d$. Their series connection therefore conducts precisely when $z$ should be zero.
By <complementary CMOS network duality>, connect this eight-device <pull-up network> between $V_{DD}$ and $z$:
$$
\boxed{
\bigl[(p(a)\parallel p(\neg c))-(p(\neg a)\parallel p(c))\bigr]
\parallel
\bigl[(p(b)\parallel p(\neg d))-(p(\neg b)\parallel p(d))\bigr].}
$$
A <PMOS transistor> conducts when its gate is zero. Consequently the first upper branch conducts when $(\neg a\lor c)\land(a\lor\neg c)$, namely $a=c$; the second conducts when $b=d$. Their parallel connection gives the required <logical disjunction>. For every stable binary input, exactly one of the <pull-up network> and <pull-down network> conducts.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2015/digital-resit-2015-cmos-network.png]
{title=Complementary <CMOS> networks: eight <PMOS transistors> above the output and eight <NMOS transistors> below it}
The figure labels each <MOSFET> channel by its gate signal; the four input <CMOS inverters> are additional to the devices drawn.
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