= Solution
The custom <CMOS> circuit uses eight <NMOS transistors> and eight <PMOS transistors> in the output networks, plus eight <transistors> in the four input <CMOS inverters>:
$$
\boxed{N=8+8+4\cdot2=24\text{ transistors}.}
$$
The complementary types give an actively driven output at either supply rail. An <NMOS transistor> provides a strong connection to ground; a <PMOS transistor> provides a strong connection to $V_{DD}$. An <NMOS transistor> used alone to pass a high level loses gate overdrive as the output rises, giving a threshold-degraded high level; the complementary problem affects a <PMOS transistor> passing a low level. Complementary networks avoid these degraded levels and, ideally, have no direct supply-to-ground conducting path for a stable input. Physical leakage and switching current remain, but a resistive load and its continuous static current are unnecessary.
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