= Solution
In the pictured single-cycle <MIPS architecture>, `RegDst` selects the write address of the <register file>: zero selects instruction bits $20\ldots16$, the `rt` field used by a load; one selects bits $15\ldots11$, the `rd` field used by an <MIPS R-type instruction>. `RegWrite` enables the clocked write to the selected <processor register>.
`ALUSrc` selects the second <ALU> input: zero uses the second <register file> read output, while one uses the sign-extended 16-<bit> immediate field. The `zero` signal is produced by the <ALU>, rather than being an opcode-decoder output: it is one exactly when the <ALU> result is zero. During `beq`, the <ALU> subtracts its operands, so `zero` tests equality. The diagram combines it with `Branch` to select the branch target instead of $PC+4$.
$$
\boxed{\operatorname{TakeBranch}=\operatorname{Branch}\land\operatorname{zero}.}
$$
Back to article page
