= Solution
Run the following two <MIPS instruction> tests separately from externally prepared states, and inspect the <register file> after the indicated instruction. External preparation is useful in a manufacturing test: code that initializes <processor registers> through the very control line being tested need not work. Assume the one potentially faulty line is `RegDst`; all other lines work normally.
For the first test, preset `$t0=7`, `$t1=5`, `$t2=99`, and execute
``
add $t2, $t0, $t1
``
The encoded `rt` is `$t1`, while `rd` is `$t2`. A healthy line or a line stuck at one writes 12 into `$t2`. A line stuck at zero instead writes 12 into `$t1`, leaving `$t2=99`.
For the second test, preset `$t3=4`, `$s0=L`, and the aligned memory word at $L$ to 37, then execute
``
lw $t3, 0($s0)
``
The zero immediate makes instruction bits $15\ldots11$ zero. A healthy line or a line stuck at zero writes 37 into `$t3`; a line stuck at one attempts to write the <MIPS zero register>, leaving `$t3=4`. The <MIPS zero register> ignores attempted writes. Thus, recording the first test's `$t2` and the second test's `$t3`,
$$
\boxed{\begin{array}{c|c}
\text{RegDst state}&(t2,t3)\\\hline
\text{normal}&(12,37)\\
\text{stuck at 0}&(99,37)\\
\text{stuck at 1}&(12,4)
\end{array}}
$$
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