= Solution
For an estimate, use the usual equal-device <CMOS> series-stack model: a $k$-input <NAND gate> or <NOR gate> has a worst-case <propagation delay> approximately $k$ times that of an inverter, because a conducting path contains $k$ series <transistors>. An <AND gate> or <OR gate> adds an output inverter. With a 1 ns inverter this gives, for $k\geq2$,
$$
\boxed{t_{\mathrm{AND},k}\simeq t_{\mathrm{OR},k}\simeq(k+1)\,\mathrm{ns}.}
$$
For $k=2$ it reproduces the stated 3 ns. This is a technology estimate under equal sizing and comparable loading, not a unique physical law inferable from a single measured delay. Actual <propagation delay> also depends on <capacitance>, <fan-out> and <transistor> sizing. If instead only the supplied two-input gates were allowed, a balanced tree would have worst-case depth $\lceil\log_2k\rceil$ and delay $3\lceil\log_2k\rceil$ ns; that is a different construction from a single $k$-input gate.
For the explicit circuit in part (a), the longest <combinational logic> path starts at $A$, passes through the shared inverter, either direction-match <exclusive or>, the <AND gate>, and the final <exclusive or> feeding $D_2$:
$$
\boxed{t_{\max}=1+2+3+2=8\,\mathrm{ns}.}
$$
The path $A\to D_1$ takes 5 ns, the paths from $B0$ or $B1$ to $D_2$ take at most 7 ns, and $B0\to D_0$ takes 1 ns. Both direction-match <exclusive or> gates act in parallel; their delays are not added together. The 8 ns excludes <clock-to-Q delay>, <setup time>, <hold time> and clock-distribution effects, because the question asks only for the <combinational logic> delay.
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