= Solution
Use a synchronous <binary counter> with three positive-edge-triggered <D flip-flops>, all driven by the same <clock signal>. Write their outputs $q_2q_1q_0$, with $q_0$ the <least significant bit>. The next-state <Boolean functions> are
$$
\boxed{D_0=\neg q_0,\qquad D_1=q_1\oplus q_0,\qquad D_2=q_2\oplus(q_1\land q_0).}
$$
Implement these with one <NOT gate>, two <exclusive or> gates, and one <AND gate>. Connect each $D_i$ to its corresponding <D flip-flop>; its output $q_i$ is address line $i$. A reset input clears all three <flip-flops> to zero, so the first selected sensor is sensor zero.
The state sequence is
$$
000\to001\to010\to011\to100\to101\to110\to111\to000.
$$
The low <bit> toggles at every <clock edge>, the middle <bit> toggles exactly when the old low <bit> is one, and the high <bit> toggles exactly when both old lower <bits> are one. These are precisely the <carry> conditions for incrementing a three-<bit> <binary representation>. Every possible state belongs to the cycle, so there is no unused state requiring recovery. Choose a <clock period> allowing the <combinational logic> to settle before the next capture.
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