= Solution
Use \b[an eight-<bit> modulo-256 <binary counter>, eight 256:1 <multiplexers>, eight data lines and eight address lines]. Thus there are \b[sixteen signal lines], apart from clock and reset, and a full scan takes 256 <clock periods>. The counter next-state equations generalize to
$$
D_0=\neg q_0,\qquad D_i=q_i\oplus\bigwedge_{j=0}^{i-1}q_j\quad(1\leq i\leq7).
$$
A 256:1 <multiplexer> for one data <bit> can be made hierarchically: 32 first-stage 8:1 <multiplexers> select within eight-sensor groups using $q_2q_1q_0$; four second-stage 8:1 <multiplexers> select groups using $q_5q_4q_3$; one final 4:1 <multiplexer> selects using $q_7q_6$. A final 8:1 <multiplexer> also works if one select input is fixed to zero and only four data inputs are used. Repeat this network eight times, sharing all selection lines. Allow for the extra <propagation delay> when choosing the <clock period>.
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