= Solution
Keep storage only for registers 1 through 31, return a hardwired all-zero word on either read port when its address is zero, and set
$$
\boxed{we_i=[\mathrm{wa}=i],\qquad i=1,\ldots,31.}
$$
There is no enable for register zero and no global RegWrite input to this <register file>. The right-hand diagram above shows this change. Every clock edge may select a write address; choosing zero suppresses all physical register enables. Consequently the <MIPS zero register> acts as a <write-suppression destination>.
Back to article page
