= Solution
Removing <logic hazards> prevents transient false control pulses, incorrect triggering of asynchronous state changes and avoidable switching activity. It also makes behavior less sensitive to unequal <propagation delays>. These benefits matter especially when an output directly controls another circuit rather than being sampled only after settling.
The usual costs are redundant <logic gates>, larger area and capacitance, more wiring and possibly a longer <critical path>. Power can rise from extra hardware even when glitch power falls. A synchronous design may instead sample after a sufficiently long clock period, trading settling time against additional hazard-correction logic. A circuit proved free of single-input static hazards need not be safe under arbitrary simultaneous input changes; <metastability> at an asynchronous input is a different problem.
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