= Solution
For the semantics stipulated by the question, \b[write $pc+4$ to register 31 and load the next $pc$ from register $rs$]. Read $rs$ through register-file output $rd_0$. Select input two of the next-PC multiplexer, which is already wired from $rd_0$. Select destination input two, already the constant register number 31, and write-back input two, already $pc+4$.
Thus the printed diagram already contains the necessary three-way <multiplexers> and wires. Extend the controller's opcode/function decoding to generate
$$
\begin{array}{c|ccccccccc}
&\mathrm{RegDst}&\mathrm{Branch}&\mathrm{Jump}&\mathrm{MemWrite}&\mathrm{MemToReg}&\mathrm{ALUOp}&\mathrm{MemRead}&\mathrm{ALUSrc}&\mathrm{RegWrite}\\\hline
\mathrm{jalr}&2&00&2&0&2&00&0&0&1
\end{array}.
$$
The displayed $\mathrm{ALUOp}$ and $\mathrm{ALUSrc}$ settings are arbitrary safe choices for an unused result. \b[No additional datapath hardware or control field is required] beyond decoding this instruction into the existing values. This uses the question's explicitly specified $pc+4$ link convention.
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