= Solution
Use the stipulated <MIPS I-type instruction> encoding, whose unused $rt$ field is zero, so register-file output $rd_1$ supplies the hardwired zero register. With $\mathrm{ALUSrc}=0$ and subtraction selected, the <arithmetic logic unit> computes $R[rs]-0$. Its <zero flag> detects $R[rs]=0$, while bit 31 of $rd_0$ is the sign in <two's complement>. Therefore the required signed test is
$$
R[rs]>0\iff\neg\mathrm{Zero}\land\neg rd_0[31].
$$
Introduce one new control bit $GT$, and replace the zero-flag input to the existing branch XOR by
$$
Z^*=\mathrm{Zero}\lor(GT\land rd_0[31]).
$$
This needs an AND gate, an OR gate and a tap of the sign bit. With $GT=0$, existing branch behavior is unchanged. With $GT=1$ and $\mathrm{Branch}=11$, the existing branch-taken circuit gives $\neg Z^*$, exactly the positive test. Its output still selects between $pc+4$ and the usual sign-extended branch target. The complete control row is
$$
\begin{array}{c|cccccccccc}
&\mathrm{RegDst}&\mathrm{Branch}&\mathrm{Jump}&\mathrm{MemWrite}&\mathrm{MemToReg}&\mathrm{ALUOp}&\mathrm{MemRead}&\mathrm{ALUSrc}&\mathrm{RegWrite}>\\\hline
\mathrm{bgtz}&-&11&0&0&-&01&0&0&0&1
\end{array}.
$$
Set $GT=0$ for each instruction in parts (a)–(c). Registers and data memory remain unchanged. The available signed `slt` operation could support a different design; the sign-and-zero design above avoids adding an ALU-input swap and explicitly distinguishes zero from positive values.
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