= Solution
The two lower conducting branches are the series pairs controlled by $a,b$ and by $c,d$. Their overall <NMOS transistor> conduction condition is $ab\lor cd$. Apply <complementary CMOS network duality>: the upper network has \b[the parallel pair of <PMOS transistors> controlled by $a,b$, in series with the parallel pair controlled by $c,d$]. Its first end connects to the high rail, its last end connects to $z$, and the junction between the two pairs is internal to the upper network.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2019/digital-systems-linear-algebra-introduction-to-formal-proof-resit-pull-up-networks.png]
{title=Original completed <pull-up networks> derived by <complementary CMOS network duality>}
The left panel gives that completion. Every upper transistor uses its correspondingly named input and conducts when that input is low. Its conducting condition is $(\neg a\lor\neg b)\land(\neg c\lor\neg d)$, exactly the complement of the lower condition. Thus the ideal static circuit connects the output to one supply rail for every stable binary input.
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