= Solution
With $K=0$, a <JK flip-flop> obeys $Q^+=J\lor Q$ at its positive <clock edge>: $J=0$ holds its old state and $J=1$ sets it. Thus each original stage is a sticky record of a previously sampled high input until Start clears it. A <D flip-flop> instead obeys $Q^+=D$, so a later sample of zero can clear the output.
Connect each replacement D input where the corresponding J input was connected, preserving the clocks and <asynchronous clear>. The first valid sequence after Start still sets both outputs. Afterwards, let $X_0$ fall and apply another rising <clock edge> to $X_1$. \b[The D version clears $Y_0$; the JK version retains $Y_0=1$.] A subsequent rising <clock edge> of $X_2$ can therefore clear $Y_1$ only in the D version. Neither circuit continuously tracks its data input between <clock edges>.
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