= Solution
The lower <NMOS transistor> network conducts through either the $a,b$ series branch or the $b,c$ series branch. Complete the upper <PMOS transistor> network by the series-parallel dual: between $V_{dd}$ and an intermediate node put $p(a)$ and $p(b)$ in parallel, and between that node and $z$ put $p(b)$ and $p(c)$ in parallel. There are \b[four upper transistors], complementing the four lower transistors. Use the usual body ties to the corresponding supply rails. Each $p(x)$ denotes a <PMOS transistor> controlled by input $x$, so it conducts when $x=0$.
The upper conducting condition is $(\neg a\lor\neg b)\land(\neg b\lor\neg c)$, exactly the complement of $ab\lor bc$. Thus for every stable input the output has a conducting path to exactly one rail in the ideal static <CMOS> model. The left panel below specifies the added network independently of the source drawing; join its lower terminal to the existing output.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2022/digital-systems-linear-algebra-introduction-to-formal-proof-resit-cmos.png]
{title=Original solution schematics: the required four-device pull-up network, and a factored six-transistor realization of the same gate. Bubbles identify PMOS gates.}
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