= Solution
Use a <synchronous sequential circuit> with four <Moore machine> states. $R$ is ready, $P$ is the one-cycle pulse state, $D$ is disabled with no qualifying final zero, and $Z$ is disabled after one sampled zero. Reset into $R$, so an initial sampled high generates a pulse immediately. The complete transition/output table is:
|| State
|| Code $q_1q_0$
|| Next if $a=0$
|| Next if $a=1$
|| $z$
| $R$
| $00$
| $R$
| $P$
| $0$
| $P$
| $10$
| $Z$
| $D$
| $1$
| $D$
| $11$
| $Z$
| $D$
| $0$
| $Z$
| $01$
| $R$
| $D$
| $0$
A particularly small implementation uses two <D flip-flops> with the next-state equations
$$
\boxed{q_1^+=a,\qquad q_0^+=q_1\lor(q_0\land a),\qquad z=q_1\land\neg q_0,\qquad(q_1,q_0)_{\rm reset}=(0,0).}
$$
Both <D flip-flops> share the clock; their outputs feed the displayed <logic gates>. The output depends only on the stored state, not combinationally on the external input. At each edge, evaluate the right-hand sides using the old state and the sampled input, then update both flip-flops together. The resulting $z$ applies throughout the following clock period.
From $R$, a high enters $P$. The next edge always leaves $P$, so the pulse lasts exactly one period. In the disabled states, a high leads to $D$ and erases progress towards rearming. A zero enters $Z$, and a second successive zero enters $R$. A later high can then enter $P$. This proves both the two-zero requirement and the startup exception. For example, sampled inputs $1,1,0,1,0,0,1,0,0,1$ yield outputs $1,0,0,0,0,0,1,0,0,1$.
\Image[/past-exam-of-the-year-1-of-the-computer-science-course-of-the-university-of-oxford/2022/digital-systems-linear-algebra-introduction-to-formal-proof-resit-rearming.png]
{title=Original Moore-state design and clocked example for the two-zero rearming pulse detector. State and output are shown after each sampling edge.}
The construction is a <synchronous pulse detector with two-zero rearming>. Assume $a$ meets setup/hold requirements at the sampling edges. A genuinely asynchronous input would first require synchronization, with its associated latency; that is separate from this sampled-input specification.
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