= PCI Express lane
{c}
A <PCI Express lane> contains one <differential signal pair>[transmit differential signal pair] and one <differential signal pair>[receive differential signal pair]. Each pair carries a serial signal, and the separate transmit and receive paths permit traffic in both directions. Multiple <PCI Express lanes>[lanes] can form a wider <PCI Express> link.<PCI Express Interface in the AMD PG213 documentation>[lane signals and lane-count configurations]{ref}
For example, an x4 link groups four <PCI Express lanes>[lanes]. At the same per-lane signaling rate it has four times the raw one-direction capacity of an x1 link, before encoding and protocol overhead. A <PCI Express lane> is not one individual <electrical conductor>[conductor], and a connector's physical size does not by itself establish the negotiated link width. <bit rate>[Payload throughput] depends on the actual width, rate, encoding and transaction traffic.
Back to article page
