= Reduced instruction set computer
{title2=RISC}
= RISC architecture
{c}
{synonym}
A processor design using a relatively regular instruction repertoire and explicit restrictions on operand forms. Immediate constants may have limited encodings, so extracting low <bits> with two <bit shifts> can avoid constructing a large <bit mask> in a temporary <processor register>. The benefit depends on the actual instruction set. A compact example appears in the <Thumb 16-bit instruction set quick reference by Arm>, whose logical <bitwise AND> instruction uses a <processor register> operand while shifts accept small immediate counts.
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